Parallel coded digit adder



June 15, 1965 R. o. GuNDERsoN ETAL 3,189,735

PARALLEL CODED DIGITADDER 6 Sheets-Sheet 1 Filed April 4. 1961 June 15,1965 R. o. GuNDl-:RsoN ETAL 3,189,735

PARALLEL CODED DIGIT ADDER 6 Sheets-Sheet 2 Q1 Filed April 4, 1961 June15, 1965 R. o. GuNDERsoN ETAL 3,189,735

PARALLEL CODED DIGIT ADDER Filed April 4. 1961 6 Sheets-Sheet 3 Y fai/elume i5 1965 R. o. GuNDERsoN ETAL 3,189,735

PARALLEL coDED DIGIT ADDER June 15, 1965 R. o. GUNDERSON ETAL 3,189,735

PARALLEL CODED DIGIT ADDER Filed April 4, 1961 l e sheets-sheet 5Mlojfvf June 15, 1965 R. o. GUNDERSON ETAL 3,189,735

PARALLEL CODED DIGIT ADDER 6 Sheets-Sheet 6 Filed April 4. 1961 UnitedStates Patent O 3,189,765 PARALLEL CODE!) DIGIT ADDER Robert 0.Gunderson, Torrance, and Tom T. Tang, Los Angeles, Calif., assignors toThe National Cash 1:Register Company, Dayton, hio, a corporation o'r'Maryland Filed Apr. 4, 1961, Ser. No. 109,735 9 Claims. (Cl. 23S-169)This invention relates to digital adding circuitry and more particularlyto an electronic adder operating in parallel fashion on binary signalsrepresenting binary coded decimal digits.

Since persons working with electronic computers are accustomed to theuse of decimal numbers, it has become the practice to design computersystems employing binary coded decimal digits, which systems must beparticularly adapted to provide appropriate interunit carry signalsbetween the particular units representative of the respective decimaldigits. In the co-pending application of Walter G. Edwards, S.N.650,275, filed April 2, 1957, and now U.S. Patent No. 2,991,009 issuedJuly 4, 1961; there is disclosed a coded digit adder unit for addingpairs of decimal digits each represented by four binary digits. Theadder unit operates by adding the binary coded signals for a pair ofdecimal digits in parallel, whereas the respective pairs of decimaldigits are added serially. The Edwards adder employs the so-calledexcess 6 code wherein the binary equivalent of the decimal digit 6 isadded to one of the operands to provide the proper binary coded sumoutput when the decimal equivalent sum is greater than the digit 9. Whenthe binary coded sum output has a decimal equivalent equal to or lessthan the digit 9, the sum is provided by a separate adder unit whichdoes not employ the excess 6 coding system and the proper sum is thenchosen from one of these two outputs by an appropriate gating system.However, the inclusion of the additional adder units requires duplicatecircuitry which inherently possesses an excessive number of components.Furthermore, with the Edwards adder unit, only one pair of binary codeddecimal digits is added at a time, and it would not be possible toconnect duplicate ones of such adder units to operate in parallel on theincoming pairs of binary coded decimal digits since the interunit carrysignal propagation is too slow to permit such operation within the timeperiod allocated for addition in a high speed electronic computer.

It is, therefore, a major object of this invention to provide a binarycoded decimal adder circuit which carries out parallel addition duringthe operation period of a pair of numbers each formed by a plurality ofbinary coded decimal digits.

It is another object of this invention to provide a parallel binarycoded digit adder which can easily be adapted to add or subtract numbersexpressed in the true binary digit code or provide for the addition orsubtraction of numbers expressed in the binary coded decimal digit code,or any other desirable binary code.

Still another object of the invention is the provision of a plurality ofadder units so adapted that all of the interunit carry signals areconcurrently generated and propagated to the next succeeding unit.

It is still another object of this invention to provide a parallel codeddecimal adder circuit having improved adder stages for optimumpropagation of the interstage carry signals as well as the sum outputsthereof.

Accordingly, the features of the invention reside in a plurality ofparallel operated adder units each adapted to receive two sets of fourbinary signals representing binary coded decimal digits, each unitincluding means to propagate to the next succeeding unit a carry signaldependent on whether the decimal equivalent of the output sum of Ficethe two sets of signals is greater than 9. In order for the carry signalto be characteristic of this decimal equivalent, one of the pairs offour binary signals is `first converted to the excess 6 code form andthe output sum from the unit in question is reconverted to a pure binarycoded decimal form when such a carry signal does not appear. In orderthat the respective interstage carry signals are quickly propagatedthroughout the plurality of the adder units, an important feature ofeach unit circuitry is that the carry signal from the preceding unit maybe transferred along an open electrical path throughout the unit,thereby requiring a minimum of delay.

Other objects of the advantages and features of the invention will bepointed out in the following description and claims and illustrated inthe accompanying drawings wherein:

FIG. l is a block diagram of the adder system illustrating thearrangement of the input and output leads and the relation of the inputand output signals to the clock pulse defining the operation of theadder system;

FIG. 2 is a schematic diagram of a typical individual unit group adaptedto receive and add two sets of four bit binary coded decimal digits;

FIG. 3 is a tabular representation illustrating the relation between thebinary coded decimal digits in Table l and the binary excess 6 system ofcoded decimal digits as shown in Table 2;

FIG. 4 is a circuit diagram of a typical binary stage used in the adderunits of the present invention;

FIG. 5 is a circuit diagram of a typical conversion stage; FIG. 6 is acircuit diagram of a conversion control;

FIG. 7 is a circuit diagram of the reconversion control;

FIG. 8 is a circuit diagram of a typical logical signal inverter;

FIG. 9 is a circuit diagram of the character setup control interposedbetween adder stages 6 and 7;

FIG. 10 is an alternative circuit of the type shown in FIG. 4;

FIG. l1 is a schematic diagram of a modiiication of the diagram in FIG.2; and

FIG. l2 is a diagram of a modification of the circuit shown in FIG. 5.

Referring now to FIG. l, there is shown a block diagram of twelve binarystage adders arranged in a three decimal unit system for the addition ofpairs of four binary digit sets of three binary coded decimal digitsdesignated as G and F. While the embodiment in FIG. 1 is designed toreceive signals representing three decimal digit numbers, larger numbersmay be accommodated by the inclusion of additional units in the system,or, if desired, with the embodiment in FIG. l, larger numbers may bebroken up into groups of three decimal digits for addition in successiveclock periods with the carry from each preceding group being supplied tocarry ip-iiop KA.

As indicated in FIG. l, the individual binary digits are represented byhigh or low potential signals Gl-Glz and IFI-F12, respectively, where ahigh voltage (0 v.) represents a true logical state of a particularsignal while the low voltage (-4 v.) represents the false state of thesignal.

IFor better understanding of the excess 6 code, there are shown, in FIG.3, tables for conversion between the `standar-d decimal coded binarysystem and the excess 6 code. Thus, the pair of input signals, G1through G4 and F1 through F4, will be represented by the mode indicatedin Table l of FIG. 3 and the signals F1 through F4 are then converted tothe excess 6 code in the form of signals H1 through H., respectively asrepresented in Table 2 of FIG. 3. After the addition is performed by theadder stages, the yadder output sum represented by signals Jal through1.14 will `automatically be equal to signals J1 through J4, i.e., in theform of the straight decimal coded binary digits -represented in Tablel, when this Vintermedimate output sum is greater than 9. However, ifthe sum is equal to 9 or less, then the adder output signa-ls will berepresentative of the form indicatedin Table 2 of FIG. 3 andreconversion of the adder output sum will take place in the reconversionstages to produce iinal outpu-t signals J1 through J4. When the `adderoutput is greater than 9, 'the respective signals are translated throughthe reconver sion stages without alteration so that the iinal output sumis always in the straight decimal coded binary digit mode'.

Since lreconversion is required whenever the intermediate output sum isequal to 9 or less, that is, when there is no carry signal K4 (or K8)produced by the fourth (or eighth) adder stage, the reconversion of theadder output sum is made dependent upon the lack of the K4 (and Kg)signal as will be more fully disclosed.`

While one of the sets of inputs will normally be converted to the excess6 code for addition .of pairs of decimal coded binary digits, the addersystem also is constructed for addition of pure binary digits, forsubtraction of either 'binary digits or coded binary digits or foraddition or subtraction .ot six bit `alpha-numeric characters. To thisend each group of four conversion stages is provided with a conversioncontrol unit that in turn is directed by signals received from theprogram control outside of the adder system but in the computer of whichthe adder system is a part. The program control signals are three innumber including an add signal (hereinafter designated as the Acsignal), and a decimal signal (hereinafter designated as the lDcsignal). The adder system is then so designed that a low logical level(-4 v.) Ac signal will set the adder vfor subtraction by complementing,while a low logical level (-4 v.) Dcr signal will set the adder forstraight binary arithmetic. In addition, a character setup signal(hereinafter designated as the Pc signal) is supplied by the programcontrol to a character setup gate between the sixth and seventh stages(see FIG; 9) of the adder -When the adderis to be set for alpha-numericoperations.

Also, the Dc signal is supplied by the program control to vthe`reconversion control so that no Lreconversion will occur when the adderis employing straight binary arithmetic.

During a particular operation of the adder of the present invention, theprogram control signals, will first reach a steady state condition whichis maintained during the operation period. lNear the beginning ofthisoperation period, then, the inputs to the various stages of therespective adder units must also corne'to a steady state condition upon-occurrence of a strobe pulse Qc to the memory during a memory readoutoperation, so that the respective output signals of the respective adderunits, as well as the memory registers, which respond to the outputsignals of the memory registers, will have obtained their proper valuesin time for the logical clock pulse CL to set the respective arithmeticregister to which the outputs of the adder units are supplied, orwhatever other means may be used to receive the adder unit outputs. TheVoperation of the adder may then be generally described as beingasynchronous and the time period of operations then, in esthe carrysignal Ka from a previous operation is to bey propagated throughout allof the stages. The adder stage circuitry constructed to` achievemini-mum de-lay of this carry signal propagation will be discussed laterin detail.

Referring to FIG. 2 there is shown a typical adder unit ot four binaryadder stages in which the input signals F1 :are transferred first toconversion stages C04 which are set in response to signals El fromconversion control CC-l di that in turn isset by the program controlsignals Ac and Dc and the input signals F2 andF3. The function .of theconversion controlwill be later described. The result of the conversion,then, are thenew signals H1' which in turn are transferred to therespective adder stages B-l. As will be described in detail later,.theadder stages B-i combine the respective'inputs, H1 and G1, with thecarry signals =K 1 from the preceding stages to produce the respectiveinterstage carries K1 and the adder outputs l' a1. lt will be noted fromthe conversion .tables in FIG. 3 `that SL11 is the same as Il yand noreconversion is required. Similarly, it will be noted from theconversion tables in tFG. 3 that in going from the excess 6- to thebinary coded decimal code, J2 is'just the inverse of Jaz and thisfunction is performed by the appropriate reeonverter stage. Similarreiations for J3 and I4 in terms Vof M2, Jag, 1:14 may be specified forthe reconversion fromthe excess 6 code to the binary coded decimal code.PThese conversions are performed by the respective reconverter` stagesin response` to the appropriate signals L2, L3, and L4 received from thereconversion control, as will be described more in detail.

Referring now to FIG. 4, the basic binary adder stage, comprised ofpairs of transistors with their bases and emitters connected to `formand` combinations of an exclusive or expression, will rst be explained.Both the adder output signal and the interstage carry signal to the nextsucceeding stage are generated by this circuit. It will be noted thatthe output signal Jai is the inverse of the normally required output sumdue to the fact that one of the input signals, H1', received from theexcess 6 converter stage is the inverse `of the normally required inputH1. However, the same circuit .willV supply the appropriate outputsignal J a1 when this adderstage receives the appropriate inputs H1andGl. r

Sinceeach of the binary adder stages Bd are similar, the followingdescription will apply to each stage which Vincludes a gating circuitcomposed Vof PNP transistors 2l and 22 that respond to the two digitalinput` signals H1 and G1. Signals Hlds supplied to both the emitter oftransistor Z1 and the `base of the transistor Z2. and signal G1 issupplied to both the.,base of transistorZl Vand the emitter oftransistor'ZZ.k The collectors of the two transistors are connected tojunction v23 and, in turn,

through line 24 to -25 volt terminals 26 by Way of or` circuit resistors25. Clam ing .diodes 27 are appropriately connected between line 24 and,-4 volt terminals 28 to clamp the line 24 at the low logical level.

This part of the circuitry functions asian exclusive or circuit inthatit `combines .two input binary signals to provide a one output only whenone of the binary input signals is one and the other is zero, conditionswhich are :stated by the expression (HGi-i-HG'V. It should be notedthatthe gating circuit uses only the binary input signals H1 and G1 withoutrequiring separate inverted signals representing the inverses.n Thustheabove expression is satisfied when the input signals are different inthat one inputv is high in potential and the other is low. It is to benoted that the two logical potential levels used in this invention are Oand -4 volts, the O volt level representing a one or high state and the-4 volt level representing a zero or low stateof the digital signal.

Transistors 2li and 2.2 each forni, whenconducting, one of the ancombinations of the output sum Vrepresented by the expression(HiGf-l-HG) which is logically equivalent to the expression in-thepreceding vparagraph. Thus, when input signal Glfis high in potentialand input signal H1' is'low in potential, junction 23 swings tothe highlogical level of 0 volts as result of current flowing from the emitterto theV collector `of transistor 22 and through resistors 25 toterminals 26. This, high potential is indicative of the and combinationHiG. Likewise when input H1 is high and input G1 is low in potential,transistor Zllconducts current'through resistors 25 to cause junction2.3` to be high which is indicative of the.and 'combination HiGl. Itshould be noted that any reverse direction current is prevented fromowing through the non-conducting transistor since the base of thenon-conducting transistor is connected to the high potential of theemitter of the conducting transistor. Also it should be noted that ifH1' and G1 are both high or are both low in potential, neither oftransistors 21 or 22 is able to conduct since the emitters and bases areconnected to the same potential. Under these conditions, current doesnot ow through resistors 25 and the low potential (-4 volt) of terminals28 is impressed on junction 23.

This potential at junction 23 is then supplied to the circuit composedof transistors 29 and 30, to form with the previ-ous carry signal K14,the adder output sum iai. This potential at junction 23 as well as theprevious carry signal K14 and the signal from transistor 22 is alsosupplied to transistor 31 to form the new carry K1.

It will be noted that the output circuit comprising transistors 29 and30 is similar in function to the circuit of tr-ansistors 121 :and 22 sothat when the carry signal K14 is high and the signal from line 24 islow, transistor 29 will produce at junction 32 a high potentialindicative of the and combination (HiG-j-HGQK4. Likewise, when the inputsignal K14 is low and the potential of the signal on line 24 is high,transistor 3i) will produce at junction 32 a high signal correspondingto the and combination (H1G}-HG1)K14 and the exclusive or combination,for Jai is expressed by the equation:

As pointed out before, this adder output sum is the inverse of anormally required sum since one of the inputs H1 is received in inverseform and it' this input were received in the form of H1, the adderoutput would be the required expression Jal. Because of the adaptationof the adder stages to the conversion and reconversion stages, theproduction of this inverse form is readily useable and need not beinverted.

Of great importance is the construction of the adder stage to propagatethe carry signal Ki to the next succeeding stage. The resultant outputto appear at junction 33 is expressed by the equation:

For this purpose, the voltage signal received at junction 23 is in turnapplied to the base of transistor 3l with the carry signal K14 from thepreceding stage being furnished to the emitter thereof to form the andcombination of these two functions, which signal is then supplied tojunction 33. The and7 combination HiGi is received from the collector oftransistor 22 as described above and supplied to junction 33. Diode 34is provided to prevent signals at junction 23 from being transferred tojunction 33. It should be pointed out that the signal received fromtransistor 22 is indicative of the function HiGi as required for thecarry signal expression only because it is the inverse signal designatedH1 which is supplied to the base of transistor 22. That is to say, itthe input signals were only representative of the terms H1 and Gi,additional circuitry would be required to create the carry signal Ki.The most important characteristic of the adder circuit however is thatwhen the base Voltage of transistor 31 is at a low state, the carrysignal K14 is propagated completely through the adder stage with aminimum delay which would not be the case in circuitry wherein the carrysignal is supplied to the base of a transistor. Because of this mode ofconstruction, when it is required to propagate such a carry signalthroughout a plurality of adder stages of the type described whichstages are arranged in relation to one another as shown in FIG. 2, therespective transistors 31 will all be in a conductive state so that sucha carry signalfwill in essence see an open electrical path throughoutthe system.

A modification of the binary adder stage of FIG. 4 is shown in FIG. l0wherein the transistors 31 and 29 are replaced by Va single transistor311 which is possible since transistor 29 perfor-ms the same function astransistor 31 but lfor difieren-t purposes. Tha-t is to say, the outputsignal from :the transistor 29 is supplied to form a part of the signalrepresenting the adder output, Ja1, while the output `from transistor.3l is supplied to forma part of the output signal .representing thecarry Ki. The circuitry shown in FIG. 10 thus has the obvious advantageof requiring .less transistors than that shown in lF-IG. 4. However, itywill be noted that the circuitry in FIG. 10 requires the :additionaldio-des 35, 36, and 37 where diode 35 prevents signa-ls from transistor31 arriving at junc- :tion 23', diode y3h prevents signals fromtransistor 3d arriving -at junction 33' :and diode 37 prevents signalsfrom transistor 22 arriving 'at junction 32'. -It should be noted whenemploying the circuitry in FIG. 10 that diode 37, as well as diodes 36and 35, provide voltage drops which must be compensated for by providingan increased voltage swing at the next :adder Stage, for example.

In the circuits of both FIG. 4 and FIIG. 10, the voltage swings atjunctions 33 and 33 are provided -by the circuitry for the nextadditional stage. For example, 4in FIG. 4, the resistor 2S and -i25 voltterminal 26 which is .adjacent diode 27 will cooperate with transistork31 of the previous adder stage. The voltage swing tor the fourth adderstage of each adder unit is in turn supplied by the llogic inverter 'Nas shown in FIG. 8.

When it is desired that the adder system =be adapted to receive pairs ofa significantly larger number of binary coded decimal digits foraddition during `a single operation, .the worst case condition, usingthe circuits of FIG. 4 or FIG. l0, for the propagation of carry signalKa to the last adder -unit would normally require a longer time period.In order t-o overcome this disadvantage, there is shown in FIG. 1'1 amodification of the unit circuitry of PIG. 2 wherein the prior carrysignal is s-imultaneously and separately supplied to each adder unit. In:this modification, the respective lbinary adder stages B-l are thesarne as in FIG. 2 and shown in detail in FIG. 4 and FIG. 10 (eitherembodiment of the adder stage may be used) with 4the one exception thatthe prior carry signal K,L is not supplied to adder stage B-l. Theintermediate output signals I1 of the respective adder stage-s, then,.dii-ier from the output signals of the adder stages in FIG. 2 in thatIthey are independent of the prior carry signal Ka. Carry ladder stagesBK-i are provided to receive the output sign-als I1 and to incorporatetherewith the prior carry signal K.,L to produce the required outputsignals Jal as normally produced by the adder stages in FIG. 2. Thecircuitry of the individual carry adder stages BK--i is just that of anexclusive or circuit as shown in FIG. l2 so that the Aoutput signal from:the collector of transistor 463' in that circuit is now representativeof the logical product Ilinm rwhere Ithe signal representing the inverseof the former term of this product is supplied to the base of transistor4d while the Vsignal represent-ing the latter term in this product issupplied to the emitter thereof. This loutput signal is thenVrepresentative of supplemental carry Kn to be supplied to the nextsucceeding carry adder stage.

Interunit carry K4 to be :supplied to unit 2 is to be representative ofthe same logical expression as 4is the K4 signal gener-ated by .adderstage B--4 in F.IG. 2. However, in the modification of FIG. l1, thecarry sign-al Ca.; received Afrom the adder stage B-'4 diiiiers from K4in that it :is not dependent on prior carry Ka. The relationship betweenK4 and Ca4 is given by the expression:

K4: Ca-i-lllzlglilacaqt To generate a signal representative of thisexpression, there is shown in block form in FIG. 11, car-ry generatorcircuit KG-4 which receives 4as inputs i-nterstage carry Ca.; `fromadder stage B44 as well as signals representing 4conversion'tables inFIG. 3.

Ythe intermediate outputs I1. While this circuit is not shown in detailit may be of the type employing conventional diode logic to pro-duce asignal representative of -a logical or combination yof a plurality oflogical and arrangements. Likewise, interunit carry signal K8 to besupplied tro unit 3 is gener-.ated by carry generator circuit KG-S andis a function of carry signal Cna as received from adder stage B--S asWell as prior carry K.,l and the respective intermediate output signals,IlLl, Since the intermediate outputs I1 a-re simultaneously generated,they are Ireadily available for supply to the respective carrygenerators. The advan-tage of the modification show-n in PIG. 11 then isthat the interunit -carry signal 4Kg Iis supplied tounit 3 and interunitcarry K4 is supplied .to unit 2 simultaneously With one another andshortly after'tbe supply of prior carry Ka to carry adder stage BK--i`of uni-t 1. Thus, it will be appreciated that an indeiinite number ofadder units may be employed with the prior carry signal being suppliedsimultaneously to each Iunit :and lthe operation `of such .a pluralityof adder units will occur within the same time interval as required foreach individual unit.

Referring again to FIG. 2, the H1 signals to be supplied to the:respective :adder stages are received from the conversion stages Co-ll-one of which exists for each adder stage. It is further noted that eachtypical unit as represented. by circuitry of FiG. 2 includes yaconversion control Which supplies the appropriate control signal El toeach conversion stage `(Doel withk the one exception that the -rstconversion stage ofeach unit receives its control signal directly fromthe program control outside yof the adder system for purposes which willbe described in the operation of the system.

In FG. 5, there is shown a typical circuit of each Co-i stage which inessence is an exclusive or circuit of the type comprising transistors 21and 212 of FIG. 4 and described in relation thereto. Thus, this circuitre- Vceives as inputs binary input signal F1 and control signal E1, theformer signal being supplied to the base of transistor dit and to theemitter of transistor di and the latter signal being supplied to theemitter transistor at) and the base transistor di. Therefore, the signalrecived at In order to perform the appropriate conversion to the excess6 code, the above expression is then in essence a function of therespective signals E1. Thus, for

`conversion stage Co-jl, the appropriate control vsignal is add signalAc as received from the program control outside the adder system (as arethe respective signals E and E9). The significance of this controlsignal is that the presence of the add signal Ac will produce as anoutput of this stage the signal HrzF', that is, a mere translation ofthe input signal F1 asindicated in the conversion tables of FlG. 3 forthe conversion from F1 to H1. Likewise, the absence of the high logicalvoltage level for add signal A,3 will eiect the output of the conversionstage CO-i to be Hi=Fi, that is the F1 Signal will be inverted asrequired for subtraction by complementing as will be described in regardto the operation of the system. y

Similarly, in order to perform the proper conversions represented inFIG. 3, the control signal E2 (as well as signals E6 and EN) isrepresentative of the and combination AcDc. That is to say, the presenceof add signal Ac and decimal signal Dc will cause converter stage Co-Zto produce the output signal H2=F2 as required by the Likewise, the lackof add signal Ac will result :in the inversion of the F2 input asrequired for subtraction by complementing While the ,Q u presence of addsignal AC and the absence of theV high logical voltage level of decimalsignal D.3 will result in an output signal from conversion stage Co-2representative of the expression iLI2=F;jY Which is just the requiredtransfer of the F2 signal as required for pure binary addition. i

Similarly, control signal E3 represents the function FZAc-l-ACDC' (andthe signals E7 and En will represent corresponding expressions). Andthecontrol signal E4 represents the expression F2F3'AC-l-ACDC as requiredfor the respective conversions of F4 for the addition and subtraction ofboth binary coded decimal digits and pure binary digits. (E8 and E12Will have'correspondingly similar expressions.) f

As explained above, the control signal El (equal to Ac) is receiveddirectly from the program control outside the adder system. Therespective control signals E2, E3, and E4, however are provided by theconversion control CC-l as shown in FIG. 6 which receives the inputsignals F2 and F3 as well as add signal Ac and decimal signal Dc asindicated in FIG. 2. In FIG. l'6, add signal Ac is suppliedto theemitter of transistor-50 as Well as to the emitters of transistors 'Siand 52 and Vdecimal signal De is supplied-to the base of transistor 5t?such that the output signal of transistor 50 is representative of theand combination ACDC whichY is the appropriate control signal E2. Theinput signalsFz and F3 are supplied respectively to the bases oftransistors 51and S3 so that the output signal from transistor 51,asreceived at junction 56 and at the emitter of transistor 53, isrepresentative of the and combinationfl-HAC and therefore the outputsignal of transistor 53 as received at junction Se is representative ofthe and-cornbination FZFSAC. The output signal from transistor 50 isalso supplied through diode 57 to junction 4S4 to producethe requiredsignal representative, of the control signal E4. The purpose of diode 57is to prevent the signal from transistor 53 from entering the ouput`lead carrying the control signal E2.

Since the signals supplied t-o the base of transistor 52 arerepresentative of the expression FZ'AC, the output from transistor 52 asreceived at junction 55 will be representative of the and combination,(FZAGYAC, which logically reduces to the expression FzAc. The outputsignal from transistor 50 is alsovsuppliedthrough diode 5t? to junctionV55V to generate the appropriate control signal E3. The purpose vofdiode 58 is to prevent signals produced by transistor 52 from enteringthe output lead representing the control signal E2.

After the respective` inputs have been combined to form the output .laffrom the adder stages, which sig- Anais are still representative of theexcess 6 code, re-

conversionV of the signals to represent Vbinary coded decimal digits isrequired whenever the sum representedV by the signals has a decimalequivalent of 9 or less. To this end, there is shown in FIG. 2 a seriesof reconversion stages R-2, R-S, and R-dorreceiving and reconverting therespective outputs of the cor-responding adder stages in dependence uponcontrol signals L2, L3, and L4 received from reconversion control RC-l.Similar recon- Vversion stages will also be employed for the respectiveadder stages B-6 through B-8 and B-ltl through B-EZ. It will be notedthat no reconversion is required for adder output Jal (as Well as L15and Iag) as illustrated in the conversion tables of FiG. 3. Each ofreconversion stages R-i is similar in nature ,to the conversion stagesCo-i exemplified bythe circuit shown in PEG.

from reconversion stage R-2 for reasons which will be explained later.Accordingly, there is shown in FIG. 12, a modiiication of the typicalreconversion stage for the case of reconversion stage R-2 (andcorresponding reconversion stages R-6 and R-10). In this modification,the output signal from transistor 40 which appears at junction 42 issupplied to the control lead L3. Diode 43' is provided to prevent theoutput signal produced by transistor 41' from also appearing at junction42.

Since the reconversion from the excess 6 code to the binary codeddecimal -form is to occur when the output sum is representative of adecimal equivalent of 9 or less, the reconversion is then determined bythe lack of a carry signal K4 from adder stage B-4 and also upon thepresence of decimal signal Dc from the program control, that is, therewill not be a reconversion whenever straight binary addition has beenperformed. As will be noted in FIG. 3, in regard to the reconversion, J2is the inverse of Jaz and thus reconversion stage R-2 will provide thecorrect reconversion when L2 equals KJqDc and wherein Kr4=K4. Statedspecifically, when there is no carry signal Kr., but there does exist adecimal signal De, L2 will equal one (1), L3 will equal zero (0) and theoutput I2' of reconversion stage R-2 will just be equal to M2.Similarly, the control signal L3 is to be representative of the fandcombination JazKrrDc and the control signal L4 is to be representativeof the expression Ja2Kr4'Dc-j-Ja3'Kr4Dc In FIG. 7 there is shown acircuitry for the reconversion control which mechanizes the respectivelogic expressions for the control signals L2 and L4. The control signalL2 is supplied to junction 66 through diode 65 wherein diodes ,'64 and65 are a standard diode logic conguration with the signal appearing atjunction 66 being representative .of the logical or combination,Kr4-j-Dc, which is yequivalent to the expression (Kr4Dc). This signal isin turn supplied to the base of transistor 62 and the base 'oftransistor 63. The signal representative of Jaz is supplied to theemitter of transistor 62 while signal Ja3 is supplied to the emitter oftransistor 63 so that the output from the collector of transistor 62 isrepresentative of the"and combination, Ia3Kr4'Dc, while the outputsignal from the collector of transistor 63 is representative of the andcombination I2Kr4Dc, with each of such output signals being supplied tojunction 67 so that the output therefrom, L4, is representative of thelogical expression, Since the control signal L3 is just taken as theoutput from the collector of transistor 40 for reconversion stage R2,this signal will be representative of the and combination Ja2Kr.Dc asindicated above.

In the circuitry so far described, the transistors have been of the PNPtype and in each case the individual transistor has been employed toproduce and combinations, the logical significance of which is dependentupon 'whether the output was at a high voltage level (0 v.) or a lowvoltage level (-4 v.). In each case then, as was vdisclosed in thedescription of the adder stage as shown ylevel to produce theappropriate voltage swing. In each case, the appropriate biasingcomponents will be found v either in the circuitry of the particularstage as described fer in one respect.

above or else in the next succeeding stage again in a manner similar tothat discussed in regard to the adder stages. v

There is one situation however in which such PNP transistors are notemployed and that is the case of the inverter-power supply stages N,live of which are employed in the adder unit circuit shown in FIG. 2.Four of the N stages are provided, one for each of the output leads toinvert the signals representing the respective l1 so that the iinaloutput is the respective J1. It will be noted in FIG. 2 that the fifth Nstage is provided to receive the carry signal K4 from adder stage B-4primarily to amplify this carry signal current. Since the stage alsoinverts the signal, additional inverter stage I is provided to receivethe current from -this N stage to supply the appropriate Kr., signal tothe reconversion control RC1 as well as to the first adder stage of thenext suceeding adder unit. The particular circuit of the respective Nstages is shown in FIG. 8 and includes NPN transistor '70. The emitterof transistor 70 is supplied with a -4 voltage and the collector thereofis connected through resistor-capacitor network 74 to junction 71 towhich 10 volts is supplied through resistor 72. The input signalsrepresenting K4 or J1 are supplied to the base of transistor 70 which isalso connected through diode 73 to a -4 voltage supply. A high signal(zero volts) representing either K., or I1 when received by the base oftransistor 70 will cause the transistor to conduct and in responsethereto junction 71 will drop from a high voltage level (zero volts)thereby producing a low voltage output representative of the inverses ofthe inputs, that is Krr lor I1.

While the discussion of the respective circuits has been made withreference to the adder and conversion stages B-l through B-4 of unitone, the same description will be representative of the circuitry ofunit 2 representing stages B-S through B-S and unit 3 representingstages B-9 through B-12. However, the circuitry of unit 2 will dif- Whenit is desired that the adder system utilize 6 bit charactersrepresenting an alpha-numeric ,code it becomes necessary to block thecarry signal between adder stages B-6 and B-7 which are similar to adderstages B-2 and B-3 in FIG. 2. To this end, there is inserted charactertix-up circuit S, which is indicated in FIG. 2 in dashed block form,between adder stages B-6 and B-7, which circuit is shown in detail inFIG. 9 and includes PNP transistor 8i) the base of which is adapted toreceive character signal Pc from the program control such that thepresence of a high voltage (0 v.) will cause transistor not to conductand the lack of which signal will leave transistor 80 open forconduction of the inner stage carry as required with binary codeddecimal operation.

Depending upon the signals Ac, Dc and Pc received from the programcontrol, the adder system thus described can perform the appropriateaddition or subtraction of binary coded decimal digits, pure binarydigits or 6 bit alpha-numeric characters and the system is so conponentsemployed are of a type now commercially available, the system hereindescribed can perform its complete operation during a time interval ofapproximately 0.7 micro-second.

When addition of 2 binary coded decimal digits is required, one set ofdigits is rst converted to the excess 6 code by the ,conversion stagesin response to add signal A, and decimal signal DE received from theprogram control. This converted form together with the other digitsignals is supplied then to the adder stages for binary addition andwhen each set of 4 output signals is representative lof a decimalequivalent sum greater than` 9, a carry signal is produced, the absenceof which will cause reconversion from the excess 6 form to standardbinary coded decimal form.` For example, in FIG. 2, there are shown tinput signals for G,=7 and F75 where the signals represent binary codeddecimal digits, add signal Ac and decimal signal Dc being received fromthe program control (there being no carry signal Ka). The conversionstages Co-lwill be set to convert the respective input signals F1 (0101)to excess 6 code and the resultant H1 (1011) will be supplied ininvertediorm H1 (0100) to adder stages B-l along with input signals G1(0111). intermediate output signals then represent the inverse form Jal(1101) and there will'be a carry out signal K4=Kr4=l- Thus the Jal'signals will be translated without change through the reconversionstages R- and inverted by the respective inverters N to produce thefinal i.

output 31 (0010), that is, the sum of the inputs G and F is 1:2 with acarry signal K=1 transmitted to unit 2.

When subtraction is desired, the conversion stages will invert the inputsignals representing the subtrahend for subtraction by the addition ofthe complement'thereof and the required additional digit, one (l), willbe Supplied by the carry source KA, the various operations being inresponse to the absence of au add signal Ac from the program control.Should the subtrahend be less than the minuend for a given pair ofbinary coded decimal digits, the added output Jai will be correctlyrepresentative of the difference and a carry signal will be produced toallow `the reconversion 'stages R-i to translate the output withoutreconversion. Should the subtrahend be greater than Vthe minuend,however, the adder output Jal will be represented in excess 6 code and acarry signal is not producedv so that reconversion of this output iseffected in the reconversion stages and the final output J1 willproperly be in straight binary coded digit form. Since reconversion isalso dependent on the presence of decimal signal De, the lack of thissignal will set the reconversion stages to translate the adder output asrequired for binary subtraction. f

When add signal Ac, but not decimal signal Dc, is` supplied by theprogram control, the system will then prot vide for pure binary additionand no reconversion will be required.` And when an alpha-numericoperation is desired, an .appropriate character setup signal Pc will besupplied to block the carry signal between respective adder stages B-6and B-7 with the resultant operations being similar to that describedabove.

By employing controlled conversion to excess 6 code of the `addend orinversion of the .subtrahend before the arithmetic operation, and thenreconverting after the arith-` metic operation when no carry signal lisgenerated for the next adder unit, the present invention embodies aunique system for both addition and subtraction of binary coded decimaldigits as well as binary numbers -and alpha-numerrie characters.Furthermore, the system requires but a single set of adder units toperform the respective operations which set may nevertheless include anunlimited number of such units without `requiring an increasedoperational time period.

While the form of the invention shown and described herein is adapted tofulfill the objects primarily stated, `it is to be understood that it isnot intended to confine the invention to the particular embodimentsdisclosed herein, for it is adaptable to embodiments in various otherforms.

What is claimed is:

1. An adder circuit for adding -a first number com- `prised of aplurality of coded digits to a second number comprised of a plurality ofcoded digits wherein each coded digit is comprised of a plurality ofbinary digits and wherein said adder circuit is` to add both the codeddigits and binary digits in parallel, said adder circuit` comprising aplurality of first sets and a plurality of secnd sets of signal inputlines, each of said sets including at least four of said input lines andadapted to receive thereon a respective one of a concurrent plurality ofiirst sets and plurality of second sets of four binary signals per setrespectively representing a Aplurality of first digits and Thev i2 aplurality of seconddigits in aiirst code system; a plurality of codingmeans for converting said concurrent iirst sets of binary signals onsaid first sets `of input lines into special coded sets of concurrentbinary signals representingsaid plurality. of first digits in a secondcode system; a plurality of simultaneously operable adder` units forconcurrently receiving the respective second sets and special codedtirst sets `ot signals, said units. `being responsive thereto toconcurrently producea plurality of sets of output signals representingin either saidrst code system or said second code system theisum of theplurality offirst digits and-the plurality of second digits; and aplurality of decoding means for respectively receiving said sets ofoutput signals for selective conversion of` tors `of both saidtransistorspto a potential source; a common output lead connected .tosaid collectors; means whereby the binary signals representingthe adderinput signals are applied 4to the. emitters and bases of saidtransistors to enable only lone of the transistors to vconduct throughsaid resistor at a time; a prior carry input line; a similar exclusiveor gating circuit adapted to receive a signal on said prior carry lineand a signal on said com- `mon output lead; a carry signal output lead;and a carry generator transistor having a base electrode connected torespond to the logical signal generated on only one of the collectors insaid first exclusive or gating circuit and having an emitter electrodeconnected to said prior carry line,` the collector of said carrygenerator transistor being connected to a carry output lead; whereby theoutput of Ysaidv similar exclusive or gating circuit is representativeof the `binary sumr of said adder input signals and the signals on said`carry .output lead is an inter stage carry signal. f v

.A 4. fA binary adder stage comprised of an exclusive or gating circuit,said gating circuit including: a firsttransistor'and second transistoreach having a base electrode, an emitter electrode and collectorelectrode; a common resistor connecting the collectors of both saidvtransistors to a potential source; a commonyoutput lead connected tosaid collectors; means whereby the binary signals representing the adderinput signals are applied to the emitters and bases of said transistorsto enable only one of the transistors to conduct through said resistorat a time; a prior carry input line; a similar exclusive or gatingcircuit adapted to receive a signal on said prior carry line and-asignal on said common output lead; a carry signal output lead; and acarry generator transistor having a base electrode connected to respondto the logical signal generated on only one of the collectors in saidfirst exclusive or gating circuit and having an emitter electrodeconnected to said prior carry line, the collector of said carrygenerator transistor being connected to a carry output leadywhereby theoutput of said similar exclusive or gating circuit is representative ofthe binary sum of said adder input signals and the signals on said carryoutput lead is an interstage carry signal.

5. A circuit for adding a first number comprised of a plurality ofbinary coded decimal digits to a Second nurnber Vcomprised of aplurality `of binary coded decimal digits whereby both the decimalandfbinary digits are added in parallel, said circuit comprising; aplurality of simultaneously operable adder units, there being one adderunit for each respective pair of binary coded decimal digits to beadded, means for applying corresponding pairs of the binary codeddecimal digits which are to be added to respective ones of said adderunits, means for converting the binary coded decimal digits of one ofsaid numbers to excess 6 binary coded decimal form prior to feeding tosaid adder units, each adder unit comprising means for performingparallel binary addition on the binary digits of the respective pair ofbinary coded decimal digits applied thereto taking into account anycarry signal applied thereto, means for applying any carry signalresulting from the binary addition in an adder unit to the nextsucceeding adder unit, and selectively operable means to which theresulting outputs from said adder units are fed in parallel forselective reconversion of the excess 6 sum represented thereby, saidreconversion means being responsive to carries produced by said adderunits.

6. The invention in accordance with claim wherein each adder unitincludes a plurality of simultaneously operable binary adder stageswherein each is able to selectively provide an essentially continuousopen electrical path therethrough for transmission of an interstagecarry signal.

7. A circuit for adding a first number comprised of a plurality ofbinary coded decimal digits to a second number comprised of a pluralityof binary coded decimal digits whereby both the decimal and binarydigits are added in parallel, said circuit comprising: a plurality ofsimultaneously operable adder units, there being one adder unit for eachrespective pair of binary coded decimal digits to be added, means forapplying corresponding pairs of the binary coded decimal digits whichare to be added to respective ones of said adder units, means forconverting the binary coded decimal digits of one of said numbers toexcess 6 binary coded decimal form prior to feeding to said adder units,each adder unit comprising a plurality of binary adder stages forperforming parallel binary addition on the binary digits of therespective pair of binary coded decimal digits applied thereto takinginto account any carry input signal applied thereto, carry generationmeans respectively associated with predetermined ones of said adderunits for generating carry input signals, means for applying a signalrepresenting carry information to a plurality of said carry generationmeans at the same time, and means applying signals to each carrygeneration means representative 4of the input binary digits applied toall previous adder units, said plurality of carry generation means beingconstructed and arranged to combine the inputs applied thereto by thelast two mentioned means so as to be able to simultaneously generate acarry input signal for each respective associated adder unit, andselectively operable means to which the resulting outputs from saidadder units are fed in parallel for selective reconversion of the excess6 sum represented thereby, said reconversion means being responsive tosaid carry input signals.

8. A circuit for adding a first plurality of coded digits to a secondplurality of coded digits wherein each coded digit is comprised lof aplurality of binary digits and wherein both the coded and binary digitsare to be added in parallel, said circuit comprising: a plurality ofsimultaneously operable adder units, there being one adder unit for eachrespective pair of binary coded digits to be added, means for applyingcorresponding pairs of the coded digits which are to be added torespective ones of said adder units, each adder unit comprising aplurality of binary adder stages for performing parallel binary additionon the binary digits of the respective pair of coded digits appliedthereto taking into account any carry input signal lli applied to theadder unit, means for applying an initial carry signal to a first adderunit, a carry generation means respectively associated with eachsucceeding adder unit for generating a carry input signal for itsrespective adder unit, means for applying said initial carry signaldirectly to each carry generation means, means applying signals to eachcarry generation means representative of the input binary digits appliedto all previous adder units Without taking into account said initialcarry, each carry generation means being constructed and arranged tocombine the inputs applied thereto by the last two mentioned means so asto be able to generate a carry input signal for each respectiveassociated adder unit without having to wait for said initial carry topropagate through any previous stages, and means cooperating with saidadder units for causing each carry input signal to properly represent acarry in the particular coding system being employed.

9. A circuit for adding a first plurality of coded digits to a secondplurality of coded digits wherein each coded digit is comprised of aplurality of binary digits and wherein both the coded and binary digitsare to be added in parallel, said circuit comprising: a plurality ofsimultaneously operable adder units, there being one adder unit for eachrespective pair of binary coded digits to be added, means for applyingcorresponding pairs -of the coded digits which are to be added torespective ones of said adder units, each adder unit including firstbinary adder means having a plurality of simultaneously operable binaryadder stages for parallel addition of the respective pair of binarycoded digits applied thereto in which the parallel addition is performedindependently of any input carry applied to the adder unit, each adderunit also including second binary adder means for parallel addition -ofthe sum of said first binary adder means with a carry input signalapplied to the adder unit, means for applying an initial carry to afirst adder unit, a carry generation means associated with eachsucceeding adder unit for generating a carry input signal for itsrespective adder unit, means for applying to each carry generation meansthe binary sum output of each of the binary stages of the first binaryadder means of all preceding adder units, means for also applying toeach carry generation means the carry output of the most significantbinary stage of the first adder means of the immediately preceding adderunit, and means for applying said initial carry directly to each carrygeneration means, each of said carry generation means being constructedand arranged to combine the inputs applied thereto by the last threementi-cned means so as to permit a carry input signal to be generatedfor its respective adder unit simultaneously with the carry inputsignals generated for the other adder units.

References Cited by the Examiner UNITED STATES PATENTS 2,705,108 3/55Stone 235-169 2,799,450 7/57 Johnson 235--176 XR 2,886,241 5/59Spaulding 23S-154 2,890,830 6/59 Woods-Hill 235-169 2,928,601 3/60Curtis 23S-169 2,981,471 4/61 Eachus 23S-169 2,991,009 7/ 61 Edwards235-169 3,001,711 9/61 Frohman 235-176 3,074,639 l/ 63 Morgan et al235--175 3,100,836 8/63 Paul et al 235--175 MALCOLM A. MORRISON, PrimaryExaminer.

WALTER W. BURNS, IR., Examiner.

